# Display signals from module JTAG
add wave -noupdate -divider {JTAG}
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_JTAG/av_address
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/av_chipselect
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/av_irq
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/av_read_n
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_JTAG/av_readdata
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/av_waitrequest
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/av_write_n
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_JTAG/av_writedata
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/dataavailable
add wave -noupdate -format Logic /test_bench/DUT/the_JTAG/readyfordata


# Display signals from module SDRAM
add wave -noupdate -divider {SDRAM}
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/az_addr
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/az_be_n
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/az_cs
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/az_data
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/az_rd_n
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/az_wr_n
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/clk
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/za_data
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/za_valid
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/za_waitrequest
add wave -noupdate -format Literal -radix ascii /test_bench/DUT/the_SDRAM/CODE
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/zs_addr
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/zs_ba
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/zs_cs_n
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/zs_ras_n
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/zs_cas_n
add wave -noupdate -format Logic /test_bench/DUT/the_SDRAM/zs_we_n
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/zs_dq
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_SDRAM/zs_dqm


# Display signals from module CPU
add wave -noupdate -divider {CPU}
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_readdata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_readdatavalid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_waitrequest
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_address
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_read
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/clk
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/reset_n
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_readdata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_waitrequest
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_irq
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_address
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_byteenable
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_read
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_write
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_writedata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/the_CPU_test_bench/W_pcb
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_CPU/the_CPU_test_bench/W_vinst
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/the_CPU_test_bench/W_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/the_CPU_test_bench/W_iw


# Display signals from module IRDA
add wave -noupdate -divider {IRDA}
add wave -noupdate -divider {  Bus Interface}
add wave -noupdate -format Logic /test_bench/DUT/the_IRDA/chipselect
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_IRDA/address
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_IRDA/writedata
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_IRDA/readdata
add wave -noupdate -divider {  Internals}
add wave -noupdate -format Logic /test_bench/DUT/the_IRDA/tx_ready
add wave -noupdate -format Literal -radix ascii /test_bench/DUT/the_IRDA/tx_data
add wave -noupdate -format Logic /test_bench/DUT/the_IRDA/rx_char_ready
add wave -noupdate -format Literal -radix ascii /test_bench/DUT/the_IRDA/rx_data


configure wave -justifyvalue right
configure wave -signalnamewidth 1
TreeUpdate [SetDefaultTree]